The use of advanced semiconductor lithography and etching processes has enabled significant reductions in the dimensions of semiconductor devices, and this has resulted in a concomitant increase in semiconductor device operating speed. These reductions in device dimensions lead to a corresponding decrease in the cross-sectional area of the device's interconnect regions. Unfortunately, these reduced interconnect regions adversely affect performance speed by increasing interconnection time delays that result from material and circuit parameters.
A solution to the problem of increased interconnection time delays involves positioning a metal silicide layer on top of a doped polycrystalline silicon in order to lower the sheet resistance of the polycrystalline silicon interconnections, and thus increase circuit speed. See, U.S. Pat. No. 4,180,596, issued Dec. 25, 1979, to Crowder et al. However, while the addition of the metal silicide layer lowers sheet resistance and thereby increases circuit speed, the dopants introduced to the polycrystalline silicon backdiffuse or outdiffuse into the metal silicide during subsequent annealing and oxidation steps. This leads to an increase in resistance of the polycrystalline silicon and creates undesirable device properties. Furthermore, with this solution, it becomes necessary to manufacture a silicide structure such that the metal atoms of a refractory metal or metal silicide are prevented from diffusing through the polysilicon and into the gate oxide during subsequent heat treatments.
As a specific example, referring now to FIG. 1, a conventional dual-gate complementary-metal-oxide-semiconductor (CMOS) device 2 with silicided gates 4,6, which is a conventional dual work-function MOSFET, is shown. The device 2 includes a gate oxide film 8 deposited on a semiconductor substrate 10, and also includes isolations 12 which function to isolate or separate the different regions of the device 2. Silicided gate 4 is situated above N-well 14 and P+ source/drain regions 16; and silicided gate 4 comprises a P+ polysilicon layer 18, a silicide layer 20 and a dielectric or insulating film 22. Silicided gate 6 is situated above P-well 24 and N+ source/drain regions 26; and silicided gate 6 comprises a polysilicon layer 28, a silicide layer 30 and a dielectric or insulating film 32. The silicide layer 30 can be comprised of a refractory metal, such as W, Ti, Ta, or a metal silicide.
A problem which is intrinsic to the conventional dual work-function MOSFET device 2 occurs due to the high temperature annealing typically applied to the polysilicon and metal silicide layers during manufacture. Since the metal silicide material has a high melting point, during such a heat treatment, metal atoms within the metal silicide layer diffuse through the polysilicon, via grain boundary diffusion, and into the gate oxide film 8. Disadvantageously, such diffusion lowers the breakdown voltage of the gate oxide film 8. As device dimensions shrink to ultra-large-scale-integration, the polysilicon layer becomes correspondingly thinner, thus exacerbating this defect.
Further, for submicron technologies, buried channel devices are extremely sensitive to problems caused by higher processing temperatures. Although the dual work-function polysilicon/silicide (polycide) structure, such as the device 2 shown in FIG. 1, offers an attractive structure for CMOS applications, the silicide acts as a diffusion sink for the dopants in the polysilicon. A strong thermodynamic driving source for metal-dopant formation leads to undesirable cross-contamination of dopants, and results in unwanted changes to gate doping levels and transistor threshold voltages.
In order to prevent the problem of metal atoms diffusing into the gate oxide, methods of depositing a diffusion barrier, such as a silicon nitride, titanium nitride, or zirconium nitride film, between the polysilicon and low resistance silicide utilizing chemical vapor deposition (CVD) have been proposed. See, for example, H. H. Chao et al., IBM Technical Disclosure Bulletin, Vol. 27, No. 11, April 1985. It is difficult, however, to deposit an ultrathin silicon nitride film by CVD with reproducibility of film thickness, and especially difficult to perform such deposition at temperatures which are adequately low for preventing changes in the electrical characteristics of the device.
U.S. Pat. No. 4,897,368, issued Jan. 30, 1990, to Kobushi et al., discloses blocking diffusion flux of metal through polysilicon using conventional ion implantation of nitrogen and oxygen to form a buried nitride/oxide layer within the polysilicon. However, such a structure is limited by the thickness of the polysilicon layer and the energy of the ion implantation.
U.S. Pat. No. 4,640,004, issued Feb. 3, 1987, to Thomas et al., discloses placement of a deposited refractory metal nitride between doped silicon and silicide, with an additional deposition of a titanium film interposed between the nitride and the polysilicon to lower contact resistance. However, such a method involves significant complexity and relies on a narrow process window of two sputtered films, wherein the process window has a very specific thickness.
U.S. Pat. No. 5,023,679, issued Jun. 11, 1991, to Shibata, discloses a polysilicon/silicon, oxide/metal silicide gate electrode with a polysilicon sidewall spacer strapping the doped polysilicon gate conductor and the lower resistivity silicide film, wherein the oxide layer functions as a diffusion barrier. However, Shibata adds complexity to the fabrication process since additional processing is required to electrically connect the polysilicon to the silicide.
Thus, there remains a need in semiconductor device technology for inhibiting the outdiffusion of dopants from polycrystalline silicon into silicide conductive layers, and for blocking the diffusion of metal from silicide conductive layers to the gate oxide layers.